Report Control Sets - 2021.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

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2021.2 English

A control set is the unique combination of a clock signal, a clock enable signal, and a set/reset signal. Each slice supports a limited number of control sets in which a combination of flip flops located in it can use. Some control set sharing is permissible within a slice depending on the architecture being used. A user should be familiar with the Configurable Logic Block architecture for the targeted family to understand what are the compatibility rules.

There are two key areas reported:

  1. The absolute number of control sets. There is a finite number of control sets in any given part. Exceeding the recommended number of control sets can have a negative impact on QoR.
  2. The load profile of control sets. When control set reduction is required, reducing control sets with a low number of loads is most effective as it adds the least amount of logic to the design.

The following is an example of the Control Sets Report Summary. You should follow recommendations in UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949) regarding recommended control set count.

Figure 1. Control Set Summary Table

Typically nets replicated at synthesis are more likely to overlap and place a higher burden on routing resources. Typically nets replicated by physical synthesis overlap less and can be ignored when calculating maximum number of control sets.

When control set counts are above the recommended level, users should reduce the count by optimizing control sets with the lowest BEL count loads. A histogram summary is reported to give an overview:

Figure 2. Control Set Histogram Table

Where more targeted information is required, the switches -hierarchical and -hierarchical_depth will help highlight specific hierarchies to target. Synthesis BLOCK_SYNTH.CONTROL_SET_THRESHOLD properties can be used to re-target control sets at a particular level of hierarchy.

The control set report also details the Flip Flop Distribution types that are used in the design. Asynchronous resets can not have their reset control re-targeted by Vivado.

Figure 3. Control Set Flip Flop Distribution

For a comprehensive list of all control sets in the design, use the -verbose switch. This lists the following information for each control set:

  • Clock Signal: The logical clock signal name
  • Enable Signal: The logical clock enable signal name
  • Set/Reset Signal: The logical set/reset signal name
  • Slice Load Count: The number of unique slices that contain cells connected to the control set
  • BEL Load Count: The number of cells connected to the control set