The Ram Utilization Report helps you analyze the utilization of dedicated
RAM blocks such as URAM and block RAM as well as Distributed RAM primitives. By default,
the report considers the entire design but it can be limited to specific hierarchies
-cell switch. The report can be generated
after synthesis and any implementation step but is only available from the Tcl command
The RAM Utilization Report is most effective on memories inferred by Vivado synthesis because you can compare the RTL Memory Array with the actual physical implementation in the FPGA.
The report shows:
- The utilization of each memory primitive
- The size of the array and the dimensions (inference only)
- The type of memory
- The utilization of the memory primitives
- The required performance of the memory
- Optional pipeline usage of the memory (where applicable)
- Worst case logical paths that start and end at the memory
- Power efficiency items such as cascading and enable rate
The report can also be generated in CSV format. This is the preferred method when you need to manage and sort a large amount of data.