To illustrate, add the following timing exceptions on the top of the previous ones:
set_max_delay 5 -to [get_ports out5] set_multicycle_path 1 -hold -to [get_cell int21_reg] set_multicycle_path 2 -setup -to [get_ports out6] set_false_path -from [get_cell int11_reg] -to [get_cell int20_reg]
All those exceptions are either already covered by a timing exception from the previous section (reporting the timing exceptions affecting the timing analysis) or target a non-existing path (there is no physical connection between the registers
After adding these four constraints, the Timing Constraints window looks like the following figure.
The Exceptions Report (
report_exceptions -ignored) is as shown in the following