Stage 3: Last Mile Timing Closure - 2021.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2021-10-27
Version
2021.2 English

The Last Mile Timing Closure stage takes the best implementation run result from either of the previous two stages and attempts to close timing on it. The design must have met the Last Mile Timing Closure requirements for the stage to be run. The QoR gain in this phase might be small compared to compile time. This is a consequence of trying to resolve issues that have a high level of difficulty in either the netlist or physical areas of the die where the timing closure challenge exists. Timing closure is achieved in approximately 20% of designs with a WNS < -0.100 ns.

The goal of the Last Mile Timing Closure stage is to close timing on the design. This is slightly different when compared to the default tool flow, which aims to achieve the best WNS possible and timing closed WHS. Algorithms must strike a balance between trying to improve timing but not altering the place and route results significantly. To achieve this, incremental compile in timing closure mode and QoR suggestions are used to close timing. Suggestions with the APPLIED property are reused from the reference run and suggestions that have the INCREMENTAL_FRIENDLY property set are applied. After routing is complete, phys_opt_design can be run to further attempt to close timing.

To enter the Last Mile Timing Closure stage from stage 2, the design must meet the following requirements:

  • Have a fully routed run from stage 1 or 2
  • Have a WNS > -0.250
  • Have a WHS > 0.000
To enter directly from stage 1, the design must meet the following requirements:
  • Have a fully routed run from stage 1
  • Have a WNS > -0.050
  • Have a WHS > 0.000

Last mile timing closure is run sequentially as a single run.