The Timing Path Summary header includes the following information:
A positive slack indicates that the path meets the path requirement, which is derived from the timing constraints. The Slack equation depends on the analysis performed.
- Max delay analysis (setup/recovery)
slack = data required time - data arrival time
- Min delay analysis (hold/removal)
slack = data arrival time - data required time
Data required and arrival times are calculated and reported in the other subsections of the timing path report.
- Max delay analysis (setup/recovery)
The path startpoint and the source clock that launches the data. The startpoint is usually the clock pin of a sequential cell or an input port.
When applicable, the second line displays the primitive and the edge sensitivity of the clock pin. It also provides the clock name and the clock edges definition (waveform and period).
The path endpoint and the destination clock that captures the data. The endpoint is usually the input data pin of the destination sequential cell or an output port. Whenever applicable, the second line displays the primitive and the edge sensitivity of the clock pin. It also provides the clock name and the clock edges definition (waveform and period).
- Path Group
The timing group that the path endpoint belongs to. This is usually the group defined by the destination clock, except for asynchronous timing checks (recovery/removal) which are grouped in the
**async_default**timing group. User-defined groups can also appear here. They are convenient for reporting purpose.
- Path Type
The type of analysis performed on this path.
- Max: indicates that the maximum delay values are used to calculate the data path delay, which corresponds to setup and recovery analysis.
- Min: indicates that the minimum delay values are used to calculate the data path delay, which corresponds to hold and removal analysis.
This line also shows which corner was used for the report: Slow or Fast.
The timing path requirement, when the startpoint and endpoint are controlled by the same clock, or by clocks with no phase-shift, is typically:
- One clock period for setup/recovery analysis.
- 0 ns for hold/removal analysis.
When the path is between two different clocks, the requirement corresponds to the smallest positive difference between any source and destination clock edges. This value is overridden by timing exception constraints such as multicycle path, max delay and min delay.
For more information on how the timing path requirement is derived from the timing constraints, Timing Paths.
- Data Path Delay
Accumulated delay through the logic section of the path. The clock delay is excluded unless the clock is used as a data. The type of delay corresponds to what the Path Type line describes.
- Logic Levels
The number of each type of primitives included in the data section of the path, excluding the startpoint and the endpoint cells.
- Clock Path Skew
The insertion delay difference between the launch edge of the source clock and the capture edge of the destination clock, plus clock pessimism correction (if any).
- Destination Clock Delay (DCD)
The accumulated delay from the destination clock source point to the endpoint of the path.
- For max delay analysis (setup/recovery), the minimum cell and net delay values are used
- For min delay analysis (hold/removal), the maximum delay values are used.
- Source Clock Delay (SCD)
The accumulated delay from the clock source point to the startpoint of the path.
- For max delay analysis (setup/recovery), the maximum cell and net delay values are used.
- For min delay analysis (hold/removal), the minimum delay values are used.
- Clock Pessimism Removal (CPR)
The absolute amount of extra clock skew introduced by the fact that source and destination clocks are reported with different types of delay even on their common circuitry.
After removing this extra pessimism, the source and destination clocks do not have any skew on their common circuitry.
For a routed design, the last common clock tree node is usually located in the routing resources used by the clock nets and is not reported in the path details.
- Clock Uncertainty
The total amount of possible time variation between any pair of clock edges.
The uncertainty comprises the computed clock jitter (system and discrete), the phase error introduced by certain hardware primitives and any clock uncertainty specified by the user in the design constraints (
The user clock uncertainty is additive to the uncertainty computed by the Vivado IDE timing engine.
- Total System Jitter (TSJ)
The combined system jitter applied to both source and destination clocks. To modify the system jitter globally, use the
set_system_jitterconstraint. The virtual clocks are ideal and therefore do not have any system jitter.
- Total Input Jitter (TIJ)
The combined input jitter of both source and destination clocks.
To define the input jitter for each primary clock individually, use the
set_input_jitterconstraint. The Vivado IDE timing engine computes the generated clocks input jitter based on their master clock jitter and the clocking resources traversed. By default, the virtual clocks are ideal and therefore do not have any jitter.
For more information on clock uncertainty and jitter, see this link in the Vivado Design Suite User Guide: Using Constraints (UG903).
- Discrete Jitter (DJ)
The amount of jitter introduced by hardware primitives such as MMCM or PLL.
The Vivado IDE timing engine computes this value based on the configuration of these cells.
- Phase Error (PE)
The amount of phase variation between two clock signals introduced by hardware primitives such as MMCM or PLL.
The Vivado IDE timing engine automatically provides this value and adds it to the clock uncertainty
- User Uncertainty (UU)
The additional uncertainty specified by the
For more information on how to use this command, see this link in the Vivado Design Suite Tcl Command Reference Guide (UG835).
Additional lines can appear in the Timing Path Summary depending on the timing constraints, the reported path, and the target device:
- Inter-SLR Compensation
The additional margin required for safely reporting paths that cross SLR boundaries in Xilinx 7 series SSI devices only.
- Input Delay
The input delay value specified by the
set_input_delayconstraint on the input port. This line does not show for paths that do not start from an input port.
- Output Delay
The output delay value specified by the
set_output_delayconstraint on the output port. This line does not show for paths that do not end to an output port.
- Timing Exception
The timing exception that covers the path. Only the exception with the highest precedence is displayed, as it is the only one affecting the timing path requirement.
For information on timing exceptions and their precedence rules, see Timing Paths.