Timing Violations - 2021.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
Release Date
2021.2 English

While analyzing and fixing the worst timing violation usually helps the overall QoR improvement, you must also review the other critical paths as they often contribute to the timing closure challenge. You can use the following command to report the 50 worst setup timing paths:

report_design_analysis -max_paths 50 -setup

The following figure shows an example of the Setup Path Characteristics table generated by this command.

Figure 1. Setup Path Characteristics

From the table, you can isolate which characteristics are introducing the timing violation for each path:

  • High logic delay percentage (Logic Delay)
    • Are there many levels of logic? (Logic Levels)
    • Are there any constraints or attributes that prevent logic optimization? (Don't Touch, Mark Debug)
    • Does the path include a cell with high logic delay such as RAMB or DSP?
    • Is the path requirement too tight for the current path topology? (Requirement)
  • High net delay percentage (Net Delay)
    • Are there any high fanout nets in the path? (High Fanout, Cumulative Fanout)
    • Are the cells assigned to several Pblocks that can be placed far apart? (PBlocks)
    • Are the cells placed far apart? (Bounding Box Size, Clock Region Distance)
    • For SSI devices, are there nets crossing SLR boundaries? (SLR Crossings)
    • Are one or several net delay values a lot higher than expected while the placement seems correct? See the section on Congestion.
  • Missing pipeline register in a RAMB or DSP cell (when present in the path)
    • Check the path to see if pipeline register is enabled for RAMBs or DSP cells
  • High skew (<-0.5 ns for setup and >0.5 ns for hold) (Clock Skew)
    • Is it a clock domain crossing path? (Start Point Clock, End Point Clock)
    • Are the clocks synchronous or asynchronous? (Clock Relationship)
    • Is the path crossing I/O columns? (IO Crossings)

    For visualizing the details of the timing paths and their placement/routing in the Xilinx® Vivado® IDE, you must use the following command:

    report_timing -max_paths 50 -setup -input_pins -name worstSetupPaths

The paths are sorted by slack and appear in the same order as in the Setup Path Characteristics table (shown in the previous figure).

The report_design_analysis command also generates a Logic Level Distribution table for the worst 1000 paths that you can use to identify the presence of longer paths in the design. The longest paths are usually optimized first by the placer in order to meet timing, which will potentially degrade the placement quality of shorter paths. You must always try to eliminate the longer paths to improve the overall QoR. The following figure shows an example of the Logic Level Distribution for a design with only one clock.

Figure 2. Logic Level Distribution Table

Based on what you find, you can improve the netlist by changing the RTL or using different synthesis options, or you can modify the timing and physical constraints.