UTIL-10: Incomplete Case Statement Increasing Control Sets - 2021.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

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2021.2 English

When case statements are incomplete, the output is forced to remember the previous state which infers a clock enable. It is recommended to define all states. For additional states, either define the output as a previously used signal or a constant 1 or constant 0 in order not to increase logic.

The following figure shows the inference of a CE LUT when state "11" is undefined.

Figure 1. CE Inference Incomplete Case