When analyzing the timing results after any implementation step with
report_design_analysis, you must review the structure of critical paths to
understand if they can be mapped to logic primitives more efficiently by modifying the
RTL, using synthesis attributes, or using different synthesis options. This is
especially important for paths with high number of logic levels, which stress the
implementation tools and limit the overall design performance.
Whenever you find a critical path with a high number of logic levels, you must question whether the functionality of the path requires so many logic levels or not. It is usually not easy to determine the optimal number of logic levels because it depends on your knowledge of the design and your knowledge of RTL optimization in general. It is a complex task to look at the post-synthesis optimized netlist and identify where the problem comes from in the RTL and how to improve it.
In project mode, the Vivado® IDE helps simplifying the analysis by providing a powerful cross-probing mechanism between the synthesized or implemented design and the elaborated design. Do the following to cross-probe the synthesized/implemented design and the elaborated design:
- Open both the synthesized/implemented design and the elaborated design in memory.
- Select the timing path in the synthesized/implemented design view and show its schematics by pressing the F4 key.
- Select the Elaborated Design in the Flow Navigator pane. The RTL cells that correspond to the timing path are also selected, so that you can open the RTL schematics (by pressing the F4 key) to view the same path in the elaborated view or trace from the endpoint pin back to the startpoint cell.
- Review the RTL logic traversed by the path, especially the size of the operators or vectors.