Before going into the details of timing analysis, it is important to understand which part of the timing reports indicates that your design is ready to run in hardware.
Important: Timing signoff is a mandatory step in the analysis of the implementation results, once your design is fully placed and routed.
By default, when using projects in the Vivado Design Suite, the runs automatically generate the text version of Report Timing Summary. You can also generate this report interactively after loading the post-implementation design checkpoint in memory.
Important: Report Timing Summary does not cover the bus skew constraints. To report the bus skew constraints, you must run the
report_bus_skewcommand separately on the command line. There is no GUI support for this command.
For a comprehensive Timing Signoff Verification methodology, see this link in the UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949).