Block RAM WRITE_MODE Power Optimizations - 2021.2 English

Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)

Document ID
UG907
Release Date
2021-10-22
Version
2021.2 English

In Xilinx® 7 series devices, for block RAMs in true dual port (TDP) mode, the WRITE_MODE can be changed from WRITE_FIRST to NO_CHANGE safely if the output of that port is not connected or the corresponding output is not needed during write operation. Similarly, for block RAM in true dual port (TDP) mode, the WRITE_MODE can be changed from READ_FIRST to NO_CHANGE safely if the corresponding output port is not connected.

In UltraScale™ devices, in addition to the above optimization, for block RAM in Simple Dual Port (SDP) mode, WRITE_MODE of both the read and write ports can be changed to NO_CHANGE safely if the read and write port clocks are asynchronous. These changes help to save power in the write cycle by not updating the output port of the block RAM. This optimization will be performed only when there is no impact to user defined functionality and performance.