Finally, monitor the activity rates across major power consuming primitives in the design. After all the above points are taken care of, the activity rates across the hard blocks such as block RAMs, GTs, and DSPs should reflect meaningful values. However, Xilinx® recommends you to double-check these values, to make sure that there are no internal logic propagation or modeling issues in the tool.
For example, one known limitation is that the Report Power does not propagate activity rates across GTs. If any GT data outputs are consumed by logic, you must set activity rates explicitly on GT TX/RX outputs.
Report Power offers a simple interface in the Report Power dialog box to set the output activity rates on various types: registers, shift registers, LUTs, RAMs, block RAMs, DSPs, and GTs. These settings are the equivalent of the -type argument of set_switching_activity command. After a value is set, it is retained for subsequent power reporting runs. Global settings affect all the instances of hard primitives in the design. For example, a Toggle Rate set on block RAMs will be applied to all the block RAMs in the design. Alternatively, the Cell Properties window could also be used to change the activity rates. In the Power Report, review block RAM, DSP, and GT sections:
To change the activity rate, select a hard block instance in the Power Report and edit the Power properties in the Cell Properties window.
Equivalent Tcl commands to change the activity rates on types:
- To set activity rates on all block RAMs in the specific design hierarchy
set_switching_activity -static_probability 0.25 -toggle_rate 10 -type bram [get_cells u1/transmit]
- To set activity rates on all the GTs present in the
set_switching_activity -static_probability 0.5 -toggle_rate 50 -type gt -all