Network on Chip (NoC) - 2021.2 English

Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)

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2021.2 English

The Versal® Network on Chip (NoC) is a high bandwidth interface within a Versal ACAP. It allows high bandwidth and Quality of Service (QoS) support for all resources on a Versal ACAP. NoC is an AXI-interconnecting network used for sharing the data among IP endpoints in the programmable logic (PL), the processing system (PS), and other hard blocks. A single physical NoC channel can be shared by traffic with different latency or bandwidth requirements. The NoC is configured using the NoC compiler to setup the required connections and the QoS. Report power uses the output of the NoC compiler automatically to estimate the power for your NoC configuration. For more information, see Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313) . The following figure shows the NoC view in the Vivado® IP integrator:

Figure 1. NoC View

The following figure shows the NoC QoS view:

Figure 2. NoC QoS View

The following figure shows the NoC Power view generated by the report power command:

Figure 3. NoC Power View
Note: NoC clock gating is enabled by default for xcvc1902, xvm1802, and xcvp1202. Hence, power is reported only for the used clock buffers in the design. Versal premium stacked silicon interconnect technology (SSIT) devices do not support NoC clock gating in the present release. Hence, all the clock buffers are used in every design.

Vivado/Vitis generates .xpe file during implementation runs as well as during NoC compiler runs. These .xpe files can be imported to the XPE tool using import functionality for performing detailed what-if analysis. For more information, see Xilinx Power Estimator User Guide for Versal ACAP (UG1275). The generated .xpe file can be found in the following path: project_1.gen/sources_1/common/nsln/NOC_Power.xpe.