Power Estimation of RF Converter - 2021.2 English

Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)

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2021.2 English
Zynq® UltraScale+™ RFSoC device family includes RF data converter subsystem. Report Power support is available for power estimation of these cores. Cores can be generated by the RF Data Converter IP which is part of the Xilinx® IP catalog in Vivado® . This facilitates for different configurations available. Using the design implemented with these IPs, Report Power can be run to generate the power report as shown in the following figures.
Figure 1. Report Power for RFADC
Figure 2. Report Power for RFDAC

Use the RF data converter IP customization to set all the user configuration values such as ADC/DAC channel count, sample rate, clock source, decimation, mixer etc. Also, the power data can be imported back to XPE sheet for further analysis of estimated power.