The device configuration settings for 7 series devices available for use with the
set_property <Setting> <Value>
tool Tcl command are shown in the following table.
|Setting||Default Value||Possible Values||Description|
|BITSTREAM.CONFIG. BPI_1ST_READ_CYCLE||1||1, 2, 3, 4||Helps synchronize BPI configuration with the timing of page mode operations in flash devices. It allows you to set the cycle number for a valid read of the first page. The BPI_page_size must be set to 4 or 8 for this option to be available.|
|BITSTREAM.CONFIG. BPI_PAGE_SIZE||1||1, 4, 8||For BPI configuration, this option lets you specify the page size which corresponds to the number of reads required per page of flash memory.|
|BITSTREAM.CONFIG. BPI_SYNC_MODE||Disable||Disable, Type1, Type2||
Sets the BPI synchronous configuration mode for different types of BPI flash devices.
Disable (the default) disables the synchronous configuration mode.
Type1 enables the synchronous configuration mode and settings to support the Micron G18(F) family.
Type2 enables the synchronous configuration mode and settings to support the Micron (Numonyx) P30 and P33 families.
|BITSTREAM.CONFIG. CCLKPIN||Pullup||Pullup, Pullnone||Adds an internal pull-up to the Cclk pin. The Pullnone setting disables the pullup.|
|BITSTREAM.CONFIG. CONFIGFALLBACK||Disable||Disable, Enable||
Enables or disables the loading of a default bitstream when a configuration attempt fails.
If the MultiBoot solution setting BITSTREAM.CONFIG.NEXT_CONFIG_ADDR is used then the BITSTREAM.CONFIG.FALLBACK setting will be enabled.
Fallback MultiBoot is not supported in Virtex-7 HT devices.
|BITSTREAM.CONFIG. CONFIGRATE||3||3, 6, 9, 12, 16, 22, 26, 33, 40, 50, 66||Uses an internal oscillator to generate the configuration clock, Cclk, when configuring in a master mode. Use this option to select the rate for Cclk.|
|BITSTREAM.CONFIG. DCIUPDATEMODE||AsRequired||AsRequired, Continuous, Quiet||Controls how often the Digitally Controlled Impedance circuit attempts to update the impedance match for DCI IOSTANDARDs.|
|BITSTREAM.CONFIG. DONEPIN 1||Pullup||Pullup, Pullnone||Adds an internal pull-up to the DONE pin. The Pullnone setting disables the pullup. Use DonePin only if you intend to connect an external pull-up resistor to this pin. The internal pull-up resistor is automatically connected if you do not use DonePin.|
|BITSTREAM.CONFIG. EXTMASTERCCLK_EN||Disable||Disable, Div-1, Div-2, Div-4, Div-8||Allows an external clock to be used as the configuration clock for all master modes. The external clock must be connected to the dual-purpose EMCCLK pin.|
|BITSTREAM.CONFIG. INITPIN 1||Pullup||Pullup, Pullnone||Specifies whether you want to add a Pullup resistor to the INIT pin, or leave the INIT pin floating.|
|BITSTREAM.CONFIG. INITSIGNALSERROR||Enable||Enable, Disable||When Enabled, the INIT_B pin asserts to '0' when a configuration error is detected.|
|BITSTREAM.CONFIG. M0PIN 1||Pullup||Pullup, Pulldown, Pullnone||Adds an internal pull-up, pull-down, or neither to the M0 pin. Select Pullnone to disable both the pull-up resistor and the pull-down resistor on the M0 pin.|
|BITSTREAM.CONFIG. M1PIN 1||Pullup||Pullup, Pulldown, Pullnone||Adds an internal pull-up, pull-down, or neither to the M1 pin. Select Pullnone to disable both the pull-up resistor and the pull-down resistor on the M1 pin.|
|BITSTREAM.CONFIG. M2PIN 1||Pullup||Pullup, Pulldown, Pullnone||Adds an internal pull-up, pull-down, or neither to the M2 pin. Select Pullnone to disable both the pull-up resistor and the pull-down resistor on the M2 pin.|
|BITSTREAM.CONFIG. NEXT_CONFIG_ADDR||None||<string>||Sets the starting address for the next configuration in a MultiBoot set up, which is stored in the WBSTAR register.|
|BITSTREAM.CONFIG. NEXT_CONFIG_REBOOT||Enable||Enable, Disable||When set to Disable the IPROG command is removed from the .bit file. This allows the Golden image to load upon power up rather than jumping to the multiboot image in a multiboot setup.|
|BITSTREAM.CONFIG. PERSIST||No||No, Yes||
Maintains the configuration logic access to the multi-function configuration pins after configuration. Primarily used to maintain the SelectMAP port after configuration for readback access, but can be used with any configuration mode. Persist is not needed for JTAG configuration since the JTAG port is dedicated and always available. PERSIST and ICAP cannot be used at the same time.
Refer to the user guide for a description. Persist is needed for Readback and Partial Reconfiguration using the SelectMAP configuration pins, and should be used when either SelectMAP or Serial modes are used.
|BITSTREAM.CONFIG. REVISIONSELECT||00||00, 01, 10, 11||Specifies the internal value of the RS[1:0] settings in the Warm Boot Start Address (WBSTAR) register for the next warm boot.|
|BITSTREAM.CONFIG. REVISIONSELECT_ TRISTATE||Disable||Disable, Enable||
Specifies whether the RS[1:0] 3-state is enabled by setting the option in the Warm Boot Start Address (WBSTAR).
0: Enable RS 3-state
1: Disable RS 3-state
|BITSTREAM.CONFIG. SELECTMAPABORT||Enable||Enable, Disable||Enables or disables the SelectMAP mode Abort sequence. If disabled, an Abort sequence on the device pins is ignored.|
|BITSTREAM.CONFIG. SPI_32BIT_ADDR||No||No, Yes||Enables SPI 32-bit address style, which is required for SPI devices with storage of 256 Mb and larger.|
|BITSTREAM.CONFIG. SPI_BUSWIDTH||NONE||NONE, 1, 2, 4||Sets the SPI bus to Dual (x2) or Quad (x4) mode for Master SPI configuration from third party SPI flash devices.|
|BITSTREAM.CONFIG. SPI_FALL_EDGE||No||No, Yes||Sets the FPGA to use a falling edge clock for SPI data capture. This improves timing margins and may allow faster clock rates for configuration.|
|BITSTREAM.CONFIG. TCKPIN 1||Pullup||Pullup, Pulldown, Pullnone||Adds a pull-up, a pull-down, or neither to the TCK pin, the JTAG test clock. The Pullnone setting shows that there is no connection to either the pull-up or the pull-down.|
|BITSTREAM.CONFIG. TDIPIN 1||Pullup||Pullup, Pulldown, Pullnone||Adds a pull-up, a pull-down, or neither to the TDI pin, the serial data input to all JTAG instructions and JTAG registers. The Pullnone setting shows that there is no connection to either the pull-up or the pull-down.|
|BITSTREAM.CONFIG. TDOPIN 1||Pullup||Pullup, Pulldown, Pullnone||Adds a pull-up, a pull-down, or neither to the TDO pin, the serial data output for all JTAG instruction and data registers. The Pullnone setting shows that there is no connection to either the pull-up or the pull-down.|
|BITSTREAM.CONFIG. TIMER_CFG||None||<8-digit hex string>||Enables the Watchdog Timer in Configuration mode and sets the value. This option cannot be used at the same time as TIMER_USR.|
|BITSTREAM.CONFIG. TIMER_USR||0x00000000||<8-digit hex string>||Enables the Watchdog Timer in Configuration mode and sets the value. This option cannot be used at the same time as TIMER_CFG.|
|BITSTREAM.CONFIG. TMSPIN 1||Pullup||Pullup, Pulldown, Pullnone||Adds a pull-up, pull-down, or neither to the TMS pin, the mode input signal to the TAP controller. The TAP controller provides the control logic for JTAG. The Pullnone setting shows that there is no connection to either the pull-up or the pull-down.|
|BITSTREAM.CONFIG. UNUSEDPIN||Pulldown||Pulldown, Pullup, Pullnone||Adds a pull-up, a pull-down, or neither to unused SelectIO™ pins (IOBs). It has no effect on dedicated configuration pins. The list of dedicated configuration pins varies depending upon the architecture. The Pullnone setting shows that there is no connection to either the pull-up or the pull-down.|
|BITSTREAM.CONFIG. USERID||0xFFFFFFFF||<8-digit hex string>||Used to identify implementation revisions. You can enter up to an 8-digit hexadecimal string in the User ID register.|
|BITSTREAM.CONFIG. USR_ACCESS||None||None, <8-digit hex string>, TIMESTAMP||Writes an 8-digit hexadecimal string, or a timestamp into the AXSS configuration register. The format of the timestamp value is ddddd MMMM yyyyyy hhhhh mmmmmm ssssss : day, month, year (year 2000 = 00000), hour, minute, seconds. The contents of this register may be directly accessed by the FPGA fabric via the USR_ACCESS primitive.|
|BITSTREAM.ENCRYPTION. ENCRYPT||No||No Yes||Encrypts the bitstream.|
|BITSTREAM.ENCRYPTION. ENCRYPTKEYSELECT||bbram||bbram, efuse||
Determines the location of the AES encryption key to be used, either from the battery-backed RAM (BBRAM) or the eFUSE register.
This property is only available when the Encrypt option is set to True.
|BITSTREAM.ENCRYPTION. HKEY||None||<hex string>||
HKey sets the HMAC authentication key for bitstream encryption. 7 series devices have an on-chip bitstream-keyed Hash Message Authentication Code (HMAC) algorithm implemented in hardware to provide additional security beyond AES decryption alone. These devices require both AES and HMAC keys to load, modify, intercept, or clone the bitstream.
To use this option, you must first set Encrypt to Yes.
|BITSTREAM.ENCRYPTION. KEY0||None||<hex string>||Key0 sets the AES encryption key for bitstream encryption. To use this option, you must first set Encrypt to Yes.|
|BITSTREAM.ENCRYPTION. KEYFILE||None||<string>||Specifies the name of the input encryption file (with a .nky file extension). To use this option, you must first set Encrypt to Yes.|
|BITSTREAM.ENCRYPTION. STARTCBC||None||<32-bit hex string>||Sets the starting cipher block chaining (CBC) value.|
|BITSTREAM.GENERAL. COMPRESS||False||True, False||Uses the multiple frame write feature in the bitstream to reduce the size of the bitstream, not just the Bitstream (.bit) file. Using Compress does not guarantee that the size of the bitstream shrinks.|
|BITSTREAM.GENERAL. CRC||Enable||Enable, Disable||
Controls the generation of a Cyclic Redundancy Check (CRC) value in the bitstream. When enabled, a unique CRC value is calculated based on bitstream contents. If the calculated CRC value does not match the CRC value in the bitstream, the device will fail to configure. When CRC is disabled a constant value is inserted in the bitstream in place of the CRC, and the device does not calculate a CRC.
The CRC default value is Enable, except when BITSTREAM.ENCRYPTION.ENCRYPT is Yes, the CRC is disabled.
|BITSTREAM.GENERAL. DEBUGBITSTREAM||No||No, Yes||
Lets you create a debug bitstream. A debug bitstream is significantly larger than a standard bitstream. DebugBitstream can be used only for master and slave serial configurations. DebugBitstream is not valid for Boundary Scan or Slave Parallel/SelectMAP. In addition to a standard bitstream, a debug bitstream offers the following features:
Writes 32 0s to the LOUT register after the synchronization word.
Loads each frame individually.
Performs a Cyclic Redundancy Check (CRC) after each frame.
Writes the frame address to the LOUT register after each frame.
|BITSTREAM.GENERAL. DISABLE_JTAG||No||No, Yes||Disables communication to the Boundary Scan (BSCAN) block via JTAG after configuration.|
|BITSTREAM.GENERAL. JTAG_XADC||Enable||Enable, Disable, StatusOnly||Enables or disables the JTAG connection to the XADC.|
|BITSTREAM.GENERAL. PERFRAMECRC||No||No, Yes||Inserts CRC values at regular intervals within bitstreams. These values validate the integrity of the incoming bitstream and can flag an error (shown on the INIT_B pin and the PRERROR port of the ICAP) prior to loading the configuration data into the device. While most appropriate for partial bitstreams, when set to Yes, this property inserts the CRC values into all bitstreams, including full device bitstreams.|
|BITSTREAM.GENERAL. XADCENHANCEDLINEARITY||Off||Off, On||Disables some built-in digital calibration features that make INL look worse than the actual analog performance.|
|BITSTREAM.READBACK. ACTIVERECONFIG||No||No, Yes||Prevents the assertions of GHIGH and GSR during configuration. This is required for the active partial reconfiguration enhancement features.|
|BITSTREAM.READBACK. ICAP_SELECT||Auto||Auto, Top, Bottom||Selects between the top and bottom ICAP ports.|
|BITSTREAM.READBACK. READBACK||False||True, False||Lets you perform the Readback function by creating the necessary readback files.|
|BITSTREAM.READBACK. SECURITY||None||None, Level1, Level2||
Specifies whether to disable Readback and Reconfiguration.
Specifying Security Level1 disables Readback. Specifying Security Level2 disables Readback and Reconfiguration.
|BITSTREAM.READBACK. XADCPARTIALRECONFIG||Disable||Disable, Enable||When Disabled XADC can work continuously during Partial Reconfiguration. When Enabled XADC works in Safe mode during partial reconfiguration.|
|BITSTREAM.STARTUP. DONEPIPE||Yes||Yes, No||Tells the FPGA device to wait on the CFG_DONE (DONE) pin to go High and then wait for the first clock edge before moving to the Done state.|
|BITSTREAM.STARTUP. DONE_CYCLE||4||4, 1, 2, 3, 5, 6, Keep||Selects the Startup phase that activates the FPGA Done signal. Done is delayed when DonePipe=Yes.|
|BITSTREAM.STARTUP. GTS_CYCLE||5||5, 1, 2, 3, 4, 6, Done, Keep||Selects the Startup phase that releases the internal 3-state control to the I/O buffers.|
|BITSTREAM.STARTUP. GWE_CYCLE||6||6, 1, 2, 3, 4, 5, Done, Keep||Selects the Startup phase that asserts the internal write enable to flip-flops, LUT RAMs, and shift registers. GWE_cycle also enables the BRAMS. Before the Startup phase, both block RAMs writing and reading are disabled.|
|BITSTREAM.STARTUP. LCK_CYCLE||NoWait||NoWait, 0, 1, 2, 3, 4, 5, 6||Selects the Startup phase to wait until DLLs/ DCMs/PLLs lock. If you select NoWait, the Startup sequence does not wait for DLLs/DCMs/PLLs to lock.|
|BITSTREAM.STARTUP. MATCH_CYCLE||Auto||Auto, NoWait, 0, 1, 2, 3, 4, 5, 6||
Specifies a stall in the Startup cycle until digitally controlled impedance (DCI) match signals are asserted. DCI matching does not begin on the Match_cycle. The Startup sequence waits in this cycle until DCI has matched. Given that there are a number of variables in determining how long it takes DCI to match, the number of CCLK cycles required to complete the Startup sequence may vary in any given system. Ideally, the configuration solution should continue driving CCLK until DONE goes high.
When the Auto setting is specified,
|BITSTREAM.STARTUP. STARTUPCLK||Cclk||Cclk, UserClk, JtagClk||
The StartupClk sequence following the configuration of a device can be synchronized to either Cclk, a User Clock, or the JTAG Clock. The default is Cclk.
Cclk lets you synchronize to an internal clock provided in the FPGA device.
UserClk lets you synchronize to a user-defined signal connected to the CLK pin of the STARTUP symbol.
JtagClk lets you synchronize to the clock provided by JTAG. This clock sequences the TAP controller which provides the control logic for JTAG.
The Spartan7 7s6 / 7s15 devices, do not support the STARTUPE2.CLK (UserClk) user startup clock pin.