- If the design does not already contain a block design, click Create Block Design under the IP integrator category in the Flow Navigator to create one.
- Click + to add new IP to the
IP integrator Canvas and type
cipsto search for the CIPS IP (as shown in the following figure). Once found, double click to add it to the IP integrator canvas.
- Once added, a green bar displays near the top of the tool bar
indicating that designer assistance is available. It is not necessary to run block
automation unless there is a need to configure additional options.
- Click the button to validate the block design, then click the button to save the block design.
- Generate the HDL wrapper for the Block Design by returning to the Project Manager, right clicking on the newly created block design and selecting Create HDL Wrapper.
- Once created, ensure this block design is instantiated as part of the design.
- Proceed with using either the Netlist Insertion Debug Probing Flow,
HDL Instantiation Debug Probing Flow, or the IP integrator Debug Flow. If the
design contains any debug cores, the AXI4 Debug
Hub will be automatically added to the netlist during
opt_designand the debug cores will be connected automaticallyNote: By default, this block design will not have any input or output ports unless additional IPs are added requiring I/O.
Note: For most applications it is not necessary to manually connect instantiated debug cores to the AXI4 Debug Hub. During
opt_design an instance of the AXI4 Debug Hub and NoC will be inserted into
the netlist and the connections between the debug cores, debug hub, and CIPS core will
be automatically stitched.
Note: For more information on design creation, simulation, and debug using the CIPS core, see Control, Interface and Processing System LogiCORE IP Product Guide (PG352).