Clearing the AES Key for UltraScale, and UltraScale+ Devices - 2021.2 English

Vivado Design Suite User Guide: Programming and Debugging

Document ID
UG908
Release Date
2021-10-22
Version
2021.2 English

To clear the AES key manually, disconnect the Vbatt pins and power-cycle the board.

Note: Pressing or pulsing the PROG pin when the board/FPGA is powered up will not clear the BBR register.

Alternatively, you can clear the AES key in Vivado IDE by right-clicking the FPGA device in the Hardware window, selecting Clear BBR Key…

Figure 1. Clearing the AES Key for UltraScale, and UltraScale+ Devices

When the Clear BBR Key dialog box appears, click OK to clear the key from the device

Figure 2. Clear BBR Key Dialog Box