The DDRMC is one of the many integrated blocks included in the Versal architecture. Upon configuring the Versal device, both the enabled and disabled memory interfaces are visible in the Vivado Hardware Manager.
Figure 1. Hardware Window with DDRMC Calibration Status
Memory calibration content is shown in a debug interface that can be used to very quickly identify calibration status and read/write window margin. This debug interface is always enabled as part of the DDRMC integrated block.
Figure 2. DDRMC Calibration Debug Interface