The Vivado Hardware Manager uses the JTAG interface to communicate with the Vivado Debug Hub core, which provides an interface between the JTAG Boundary Scan (BSCAN) interface of the FPGA device and the Vivado Debug cores.
- JTAG Clock
- This clock synchronizes the internal state machine operation of the JTAG
Boundary Scan (BSCAN) interface. You will typically choose the JTAG clock
frequency in the Vivado Hardware Manager while connecting to the target device.
If your design contains debug cores, ensure that the JTAG clock is 2.5x times
slower than the debug hub clock.
You can modify the JTAG frequency by using the Open New Hardware Target wizard or the following Tcl command:
set_property PARAM.FREQUENCY 250000 [get_hw_targets */xilinx_tcf/Digilent/210203327962A]
- Debug Hub Clock
The Vivado Debug Hub core, which provides an interface between the JTAG Boundary Scan (BSCAN) interface of the FPGA device and the Vivado Debug cores. The Debug Hub core is inserted automatically by the Vivado IDE during the design implementation step if it detects debug cores in the design. The Vivado IDE chooses the clock driving the Debug Hub core during the design implementation step.
Xilinx recommends that the Debug Hub clock frequency be around 100 MHz or less because the JTAG clock speeds do not require a particularly high frequency.
You can change the Debug Hub Clock using the following TCL command.
connect_debug_port dbg_hub/clk [get_nets <clock net name>]Note: You need to run this command after the design has been synthesized, but before implementation.
You can also reduce the Debug Hub Clock Frequency to a 100 MHz using the following TCL commands.
set_property C_CLK_INPUT_FREQ_HZ 200000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER true [get_debug_cores dbg_hub]Note: You need to run this command after the design has been synthesized, but before implementation. This is recommended for designs which have very high speed clocks. This command enables the inclusion of an MMCM based clock divider inside of the Debug Hub core to achieve a clock frequency of 100 MHz.