The System ILA IP in Vivado IP integrator allows you to perform in-system debugging of post-implemented designs on an FPGA or ACAP. Use this feature when you need to monitor interfaces and signals in the IP integrator Block Design. This feature enables you to debug AXI Read and Write Transactions in addition to AXI Read and Write, Data, and Address channel events in the Vivado Hardware Manager.
Note: On Versal devices, all System ILA features are now supported using the ILA core and can be selected by changing the ILA Input Type from
See this link in the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994) for the steps to debug interfaces and/or nets in the Block Design.