The System ILA IP in IP integrator allows you to perform in-system debugging of designs on an FPGA. On Versal devices, the System ILA core is obsolete. Interface debugging is now supported in the standard ILA with AXIS interface. Use this feature when there is a need to monitor interfaces and signals in the IP integrator Block Design.
See this link in the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994) for the steps to debug interfaces and/or nets in the Block Design.
If you have instantiated System ILA debug cores in your IP integrator Block Design, you can debug and monitor AXI transactions and their corresponding read and write events in the waveform window.