The first phase of getting a suitable hardware design to help debug and validate your system's high-speed serial I/O interfaces is to generate the IBERT core. The following steps outline how to do this:
- Open the Vivado IDE.
- On the first panel, choose Next when the Open IP Catalog wizard opens. , then click
- Select the desired part, target language, target simulator, and IP location. Click Finish.
- In the IP Catalog under , you will find one or more available IBERT cores as shown in the following figure, depending on the device selected in the previous step.
- Double-click the desire IBERT architecture to open the Customize IP Wizard for that core.
Customize the IBERT core for your given hardware system requirements. For details on the various IBERT cores available, see the following IP Documents:
- Integrated Bit Error Ratio Tester 7 Series GTX Transceivers LogiCORE IP Product Guide (PG132)
- Integrated Bit Error Ratio Tester 7 Series GTP Transceivers LogiCORE IP Product Guide (PG133)
- Integrated Bit Error Ratio Tester 7 Series GTH Transceivers LogiCORE IP Product Guide (PG152)