IBERT - 2021.2 English

Vivado Design Suite User Guide: Programming and Debugging

Document ID
UG908
Release Date
2021-10-22
Version
2021.2 English

The Integrated Bit Error Ratio Tester (IBERT) Serial Analyzer design enables in-system serial I/O validation and debug. This allows you to measure and optimize your high-speed serial I/O links in your FPGA-based system. Xilinx recommends using the IBERT Serial Analyzer design when you are interested in addressing a range of in-system debug and validation problems from simple clocking and connectivity issues to complex margin analysis and channel optimization issues.

Xilinx recommends using the IBERT Serial Analyzer design when you are interested in measuring the quality of a signal after a receiver equalization has been applied to the received signal. This ensures that you are measuring at the optimal point in the TX-to-RX channel thereby ensuring real and accurate data. Users can access this design by selecting, configuring, and generating the IBERT core from the IP Catalog and selecting the Open Example Design feature of this core. See Serial I/O Hardware Debugging Flows and Debugging the Serial I/O Design in Hardware for more details on the IBERT core and its usage methodology in the Vivado Design Suite.