The configuration of the ILA core has an impact in meeting the overall design timing goals. Follow the recommendations below to minimize the impact on timing:
- Choose probe width judiciously. The bigger the probe width the greater the impact on both resource utilization and timing.
- Choose ILA core data depth judiciously. The bigger the data depth, the greater the impact on both block RAM resource utilization and timing.
- Ensure that the clocks chosen for the ILA cores are free-running clocks. Failure to do so could result in an inability to communicate with the debug core when the design is loaded onto the device.
- Close timing on the design prior to adding the debug cores. Xilinx does not recommend using the debug cores to debug timing related issues.
- Make sure the clock input to the ILA core is synchronous to the signals being probed. Failure to do so results in timing issues and communication failures with the debug core when the design is programmed into the device.
- Make sure that the design meets timing before running it on hardware. Failure to do so results in unreliable results.
For Non-Versal architectures: Ensure that the clock going to the
dbg_hubis a free running clock. Failure to do so could result in an inability to communicate with the debug core when the design is loaded onto the device. You can use the
connect_debug_portTcl command to connect the
clkpin of the debug hub to a free-running clock.
For Non-Versal architectures: If you still notice that
timing has degraded due to adding the ILA debug core, and the critical path is
dbg_hub, perform the following steps:
- Open the synthesized design.
- Find the
dbg_hubcell in the netlist.
- Go to the Properties of the
- Find property
- Set it to frequency (in Hz) of the clock that is
connected to the
- Find property
C_ENABLE_CLK_DIVIDERand enable it.
- Re-implement design.