Modifying Properties on the Debug Cores - 2021.2 English

Vivado Design Suite User Guide: Programming and Debugging

Document ID
UG908
Release Date
2021-10-22
Version
2021.2 English

Each debug core has properties you can change to customize its behavior. To learn how to change properties on the debug_core_hub debug core, refer to Changing the BSCAN User Scan Chain of the Debug Core Hub.

You can also change properties on the ILA debug core. For example, to change the number of samples captured by the ILA debug core, do the following:

  1. In the Debug window, select the desired ILA core (such as u_ila_0).
  2. In the Cell Properties window, select the Debug Core Options view.
  3. Using the C_DATA_DEPTH pull-down list, select the desired number of samples to be captured.

A full description of all ILA core properties can be found in the following table.

Table 1. ILA Debug Core Properties
Debug Core Property Description Possible Values
C_DATA_DEPTH Maximum number of data samples that can be stored by the ILA core. If you increase this value it can consume more block RAM in the ILA core and adversely affect design performance.

1024 (Default)

2048

4096

8192

16384

32768

65536

131072

C_TRIGIN_EN Enables the TRIG_IN and TRIG_IN_ACK ports of the ILA core. Note that you need to use the advanced netlist change commands to connect these ports to nets in your design. If you want to use the ILA trigger input or output signals, consider using the HDL instantiation method of adding ILA cores to your design.

false (Default)

true

C_TRIGOUT_EN Enables the TRIG_OUT and TRIG_OUT_ACK ports of the ILA core. Note that you need to use the advanced netlist change commands to connect these ports to nets in your design. If you want to use the ILA trigger input or output signals, consider using the HDL instantiation method of adding ILA cores to your design.

false (Default)

true

C_ADV_TRIGGER Enables the advanced trigger mode of the ILA core. Refer to Debugging Logic Designs in Hardware for more details about this feature.

false (Default)

true

C_MEMORY_TYPE (Versal Only) Selects the memory primitive (BlockRAM or UltraRAM) to use for the AXIS-ILA trace memory. Targeting UltraRAM can be useful for designs with high Block RAM utilization.

0 (BRAM)

1 (URAM)

C_INPUT_PIPE_STAGES Enables extra levels of pipe stages (for example, flip-flop registers) on the PROBE inputs of the ILA core. You can use this feature to improve timing performance of your design by allowing the Vivado tools to place the ILA core away from critical sections of the design.

0 (Default)

1

2

3

4

5

6

C_EN_STRG_QUAL Enables the basic capture control mode of the ILA core. Refer to Debugging Logic Designs in Hardware for more details about this feature.

false (Default)

true

C_ALL_PROBE_SAME_MU Enables all PROBE inputs of the ILA core to have the same number of comparators (also called "match units"). This property should always be set to true.

true (Default)

false (not recommended)

C_ALL_PROBE_SAME_MU_CNT

The number of comparators (or match units) per PROBE input of the ILA core. The number of comparators that are required depends on the settings of the C_ADV_TRIGGER and C_EN_STRG_QUAL properties:

If C_ADV_TRIGGER is false and C_EN_STRG_QUAL is false, can be set to 1 through 16.

If C_ADV_TRIGGER is false and C_EN_STRG_QUAL is true, can be set to 2 through 16.

If C_ADV_TRIGGER is true and C_EN_STRG_QUAL is false, can be set to 1 through 16.

If C_ADV_TRIGGER is true and C_EN_STRG_QUAL is true, can be set to 2 through 16.

IMPORTANT: if you do not follow the rules above, you will encounter an error during implementation when the ILA core is generated.

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