The Debug Bridge IP supports the setup and configuration of multiple independent debug trees in a design. You can use multiple independent debug trees in applications where it is desirable to make specific debug logic visible to certain users (e.g., system administrators) while hiding it from other users. This feature supports the setup of independent debug trees both in a standalone and Dynamic Function eXchange design. Each of these independent debug trees can be connected to any of the supported debug cores (e.g. ILAs, VIOs etc).
To enable this feature, you need to instantiate one Debug Bridge IP in the appropriate mode, either the "From AXI to BSCAN" or "From PCIe to BSCAN" mode, for each of the debug trees you want to enable. For instance, in a data center design where multiple classes of users will access the DUT, you can instantiate a "From AXI to BSCAN" Debug Bridge IP in the customer-visible address map while instantiating a second "From AXI to BSCAN" Debug Bridge IP in the administrator-visible address map.
When the administrator and/or the customer are ready to debug the design, they will only have to connect to the debug bridge using the Vivado Hardware Manager at the correct device offset depending on how they are communicating with the debug cores (i.e. PCIe or JTAG pins). For more information on using the XVC flow with the PCIe core and Debug Bridge in this mode, and for an example design refer to UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213).
Below is a table listing the different Debug Bridge modes and features available in those modes:
|Debug Bridge Mode||XVC Support||Can be used In Reconfigurable Partition||JTAG Fallback Support||MDM Support|
|From AXI to BSCAN||Yes||Yes 1||Yes 2||Yes 3|
|From JTAG to BSCAN||Yes||Yes 1||Yes 2||Yes 3|
|From PCIe to BSCAN||Yes||Yes 1||Yes 2||Yes 3|
|From PCIe to JTAG||Yes||Yes 1||NA||NA|
|From BSCAN to DebugHub||No||Yes 1||NA||Yes 3|
|BSCAN Primitive||No||No||NA||Yes 3|
|From AXI to JTAG||Yes||Yes||NA||NA|
Below is an illustration of a design with the XVC Debug Bridge in an RP.
This is a PR design with two reconfigurable partitions, Counter RP and Shifter RPs. This figure illustrates the different Debug Bridge modes used in both static and RP regions.
The static partition of design has two Debug Bridge IPs. The first Debug Bridge IP is in BSCAN Primitive mode and configured to have three BSCAN master interfaces. Two of the BSCAN master interfaces are connected to the Debug Bridge instances in Counter-RP and Shifter-RP partitions providing a parallel path for debug. The third BSCAN master interface is connected to another Debug Bridge instance within the static partition configured in the From BSCAN to Debug Hub mode. The Debug Bridge configured in From BSCAN to Debug Hub mode can communicates to the various Debug IPs (ILA, VIO, JTAG-to-AXI, etc.) in the design, which in this case is the ILA IP.
In this system the Counter-RP partition contains a Debug Bridge instantiated in the AXI-to-BSCAN mode. You can use this Debug Bridge in XVC mode, the Debug Bridge receives XVC Commands via AXI4-Lite interface. This Debug Bridge can further communicate with other Debug Bridge instances in the design via the Soft-BSCAN (Boundary Scan) interface. Since this Debug Bridge is configured to contain two BSCAN master interfaces it communicates with the MDM and the Debug Bridge instance configured in From BSCAN to Debug Hub mode. The Debug Bridge configured in From BSCAN to Debug Hub mode can communicates to the various Debug IPs (ILA, VIO, JTAG-to-AXI etc.) in the design, which in this case is the ILA IP.
On the other hand, the Shifter-RP partition contains only one Debug Bridge instance configured in From BSCAN to Debug Hub mode that can communicate with the various Debug IPs (ILA, VIO, JTAG-to-AXI etc.) in the design, which in this case is the ILA IP.
For more information see the Debug Bridge LogiCORE IP Product Guide (PG245).
An illustration of some of the Debug Bridge modes is presented below.