Upon configuring the device, if enabled, the PCI Express cores are visible in the Vivado Hardware Manager.
The PCI Express LTSSM debug content will be shown in an LTSSM State Transition Diagram. This interface displays an ordered list of the LTSSM state transitions showing which states have been visited as well as a diagram illustrating the visited states and currently occupied state in the LTSSM.
Figure 1. PCI Express Link Debug Interface