The VIO cores that you add to your design appear in the Hardware window under the target device. If you do not see the VIO cores appear, right-click the device and select Refresh Hardware. This re-scans the FPGA or ACAP and refreshes the Hardware window.
Click the VIO core (called hw_vio_1 in the following figure) to see its properties in the VIO Core Properties window. By selecting the VIO core, you should also see the probes corresponding to the VIO core in the Debug Probes window as well as the corresponding VIO Dashboard in the Vivado IDE workspace (see the following figure).
The VIO core can become out-of-sync with the Vivado IDE. Refer to Viewing the VIO Core Status for more information on how to interpret the VIO status indicators.
The VIO core operates on an object property-based set/commit and refresh/get model:
- To read VIO input probe values, first refresh the hw_vio object with the VIO core values. Observe the input probe values by getting the property values of the corresponding hw_probe object. Refer to the section called Interacting with VIO Core Input Probes for more information.
- To write VIO output probe values, first set the desired value as a property on the hw_probe object. These property values are then committed to the VIO core in hardware in order to write these values to the output probe ports of the core. Refer to the section called Interacting with VIO Core Input Probes for more information.