The Vivado® serial I/O analyzer feature is used to interact with IBERT debug IP cores that are in your design. To access the Vivado serial I/O analyzer feature, click the Open Hardware Manager button in the Program and Debug section of the Flow Navigator.
The steps to debug your design in hardware are:
- Connect to the hardware target and programming the FPGA with the bit file.
- Create Links.
- Modify link settings and examine status.
- Run scans as needed.