Note: The following method for eFUSE access and programming is not supported on MPSoC and Versal devices.
7 series, UltraScale, and UltraScale+ devices have one-time programmable bits called eFUSE bits that perform specific functions. The different eFUSE bit types are as follows:
- FUSE_DNA - Stores unique device identifier bits (non-programmable).
- FUSE_USER - Stores a 32-bit user-defined code.
- FUSE_KEY - Stores a key for use by the AES bitstream decryptor.
- FUSE_CNTL - Controls key use and read/write access to eFUSE registers.
- FUSE_SEC - Controls special device security settings in UltraScale and
UltraScale+ devices. Important: Programming eFUSE register bits is a one-time only operation. Once eFUSE register bits are programmed (i.e., from unprogrammed state 0 to programmed 1 state), they cannot be reset to 0 and/or programmed again. You should take great care to double-check your settings before programming any eFUSE registers.CAUTION:If any eFUSE register bits have been previously programmed (i.e., from unprogrammed state 0 to programmed state 1) and an attempt is made to program them again, the Vivado hardware manager issues a critical warning indicating that some bits have already been programmed. However, despite this warning, subsequent eFUSE register bits that have not been programmed during the previous operation (in unprogrammed state 0) will be programmed.Important: Xilinx recommends programming the FUSE_USER, FUSE_KEY, and FUSE_RSA registers first, then rerunning the eFUSE programming wizard to program the FUSE_SEC bits to control the FPGA security settings, and then finally, the FUSE_CNTL bits to control read/write access to these eFUSE bits.