Most of the clocking guidelines of UltraScale+ stay same for Versal. However, Versal Clocking structure provides more clocking primitives and guidelines for better management of skew and meeting timing closure more easily. Refer Design Creation: Clocking Guidelines section in Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387) for the detailed understanding of clocking structure in Versal.
|Internal clocks||Clocks with driver and loads inside the reconfigurable partition|
|Boundary clocks||Clocks with nets crossing the reconfigurable module’s cell boundary
DFX behavior for different categories of clock nets is as follows:
Internal RM Clock Net
- Clock root is placed at the center of loads inside RP Pblock.
- More flexibility for placement and routability of the internal clock of RM in subsequent implementation
- This is recommended whenever possible to achieve better skew and optimal clock root placement.
Boundary Clock Net
- Boundary clock net track gets locked down after first implementation.
- The PPLOCs of the boundary clock nets are distributed to all clock regions covered by the RP Pblock.
- The clock root of the boundary clock net can get placed anywhere in the device, since it can drive both static and RP loads. If the loads of boundary clock are more in static region, it is possible that clock root gets placed in static region.
- If the first implementation is done using training logic in the RP Pblock,
it is possible that boundary clock nets gets locked down after first
implementation with sub-optimal clock root location. Xilinx recommends using
USER_CLOCK_ROOTconstraint on the boundary clock net to manually constrain the