Dynamic Function eXchange (DFX) allows for the reconfiguration of modules within an active design. This flow requires the implementation of multiple configurations, which ultimately results in full bitstreams for each configuration and partial bitstreams for each reconfigurable module (RM). The number of configurations required varies by the number of modules that need to be implemented. However, all configurations use the same top-level, or static, placement and routing results. These static results are exported from the initial configuration and imported by all subsequent configurations using checkpoints.
DFX is a comprehensive solution that is comprised of many parts. These elements include the Xilinx® silicon ability to be dynamically reconfigured, the Vivado® software flow for compiling designs from RTL to bitstream, and the complementary features such as IP. In this release, you will see a mix of DFX and Partial Reconfiguration (PR) terminology, with DFX representing the overall solution and PR representing a component technology piece of that solution.
Complementary documentation, such as application notes, white papers, and videos, will not be recaptured with DFX terminology, but all new documentation from 2020 on will show the DFX terms.
The content of this guide includes the following:
- Description of Dynamic Function eXchange as implemented in the Vivado® Design Suite
- Assumption of familiarity with FPGA design software, particularly Vivado Design Suite
- Updates specific to the Vivado Design Suite Release 2021.2. This release supports Dynamic
Function eXchange for the products listed below. For a complete list of supported
devices, see List of Supported Devices.
7 series Devices
- Nearly all
devices.Note: Spartan-7 devices, as well as Artix-7 A12T and 7A25T, are not supported.
- Nearly all Virtex®-7, Kintex®-7, Artix®-7, and Zynq®-7000 SoC devices.
- Place and route, as well as bitstream generation is
enabled for all production devices.Note: Expect memory usage to be higher for VU440 than all others (potentially exceeding 64 MB).
- Bitstream generation is disabled by default for ES2 devices, but place and route can still be performed.
- Place and route, as well as bitstream generation is enabled for all production devices.
- Place and route, as well as bitstream generation, is enabled for all production devices, including all Zynq UltraScale+ RFSoCs, the Virtex UltraScale+ VU57P, and the Kintex® UltraScale+™ KU19P.
- Support for all four Artix UltraScale+ devices is included in this release. The two larger devices (AU25P, AU20P) are production, while the two smaller devices (AU15P, AU10P) are early access with bitstream generation gated by default.
- Place and route is enabled for many engineering silicon (ES1, ES2) versions of UltraScale+ devices. Bitstream generation is disabled by default for these devices.
- DFX support for Versal devices is production for three devices in this release: the Versal AI Core VC1902, VC1802, and the Versal Prime VM1802. Two additional Versal Prime devices (VM1402, VM1302) are included as early access.
- Versal Premium devices (VP1202, VP1502, VP1702 and VP1802) are available for ES1 silicon. All of these devices are limited early access with license-gated implementation and parameter-gated device image generation. Contact Xilinx support if access to any of these devices are needed.
- 7 series Devices