The unique device structure of Versal ACAP open new opportunities for dynamic reconfiguration and related solutions. Versal-specific use cases are listed in this section.
Classic SoC Boot
Classic SoC Boot solution enable designers to boot the processors in the Scalar Engines of a Versal device and access DDR memory before the programmable logic (PL) in the Adaptable Engines is configured. This allows DDR-based software like Linux to boot first followed by the PL, which can configured later if needed via any primary or secondary boot device or through a DDR image store. The Classic SoC Boot feature is intended to treat Versal boot sequences similar to Zynq UltraScale+ MPSoCs. This solution is built using a Dynamic Function eXchange flow through the Vivado IP integrator, which includes automatic floorplan generation and flow-specific design rule checks (DRCs). The entire PL is dynamic and can be completely reloaded while any operating system and DDR memory access remain active.Classic SoC Boot is incompatible with use of the CPM, including PCIe controller, DMA features, and dynamic reconfiguration of sub-regions of the PL is not yet supported. For more information on Classic SoC Boot including design requirements and a tutorial walkthrough, see the Classic SoC Boot Tutorial available from the Xilinx GitHub repository.