By default, the Vivado® simulator adds simulation objects from the testbench to the Waveform window. In the case of this tutorial, the following testbench signals load automatically:
- Differential clock signals (
sys_clk_n). This is a 200 MHz clock generated by the testbench and is the input clock for the complete design.
- Reset signal (
reset). Provides control to reset the circuit.
- GPIO buttons (
gpio_buttons[1:0]). Provides control signals to select different frequency sine waves.
- GPIO switch (
gpio_switch). Provides a control switch to enable or disable debouncer logic.
- LEDs (
leds_n[3:0]). A placeholder bus to display the results of the simulation.
You add some new signals to this list to monitor those signals as well.
If necessary, in the Scopes window, click the sign to expand the testbench. (It might be expanded by default.)
An HDL scope, or scope, is defined by a declarative region in the HDL code, such as a module, function, task, process, or named blocks in Verilog. VHDL scopes include entity/architecture definitions, blocks, functions, procedures, and processes.
- In the Scopes window, click to select the dut object.
The current scope of the simulation changes from the whole testbench to the selected object. The Objects window updates with all the signals and constants of the selected scope, as shown in figure below.
- From the Objects window, select signals
sineSel[1:0]and add them into Wave Configuration window using one of the following methods:
- Drag and drop the selected signals into the Waveform window.
- Right-click on the signal to open the popup menu, and select Add to Wave Window.