Create a new project for managing source files, add IP to the design, and run behavioral simulation:
- On Windows, launch the Vivado IDE by
(x denotes the latest version of Vivado 2021 IDE)Note: Your Vivado ML Editions installation might be called something other than Xilinx® Design Tools on the Start menu.
- In the Vivado IDE Getting started page, click Create Project.
- In the New project dialog box, click Next and enter a project name: project_xsim.
- For the Project Location, browse to the folder containing the extracted
tutorial data, <Extract_Dir>. Make
sure to check the Create project subdirectory option and click Next.
Note: Create project subdirectory option is preselected.
- In the Project Type dialog box, select RTL
Project and click Next.
- In the Add Source dialog box, click Add Directories
and add the extracted tutorial design data:
Note: You can press the Ctrl key to click and select multiple files or directories.
- Set the Target Language to Verilog to indicate the netlist language for synthesis.
- Set the Simulator Language to Mixed as shown in the following figure.
The Simulator Language indicates which languages the logic simulator supports or requires. Vivado Design Site ensures the availability of simulation models of any IP cores in the design by using the available synthesis files to generate the required language-specific structural simulation model when generating output targets. For more information on working with IP cores and the Xilinx IP catalog, refer to the Vivado Design Suite User Guide: Designing with IP (UG896). You can also work through the Vivado Design Suite Tutorial: Designing with IP (UG939).
- Click Next.
- Click Next to bypass the Add
Constraints dialog box.
In the Default Part dialog box shown in the following figure, select Boards, and then select either Kintex®-7 KC705 Evaluation Platform for 7 series or Kintex-UltraScale KCU105 Evaluation Platform for UltraScale devices and click Next.