Step 2: Adding IP from the IP Catalog - 2021.2 English

Vivado Design Suite Tutorial: Logic Simulation
Document ID
UG937
Release Date
2021-11-10
Version
2021.2 English
The Sources window displays the source files that you have added during project creation. The Hierarchy tab displays the hierarchical view of the source files.
  1. Click the icon in the Sources window to expand the folders as shown in the following figure. Expand all button can be used to view all the files at all levels of hierarchy.

    Notice that the Sine wave generator (sinegen.vhd) references cells that are not found in the current design sources. In the Sources window, the missing design sources are marked by the missing source icon .

    Note: The missing source icon is used to view only the missing sources. This is useful in viewing the missing sources in larger designs.

    Now, add the sine_high, sine_mid, and sine_low modules to the project from the Xilinx IP catalog.