At this point in your Tcl
script, you want to read the XDC file, using
read_xdc, which is
used in both synthesis and implementation.
- Add the following to your Tcl
The design is now ready for synthesis.
In Non-Project Mode, unlike Project Mode, there are no design runs to launch, and no runs infrastructure managing the strategies used and the state of the design. You will manually launch the various stages of synthesis and implementation.
- For synthesis, you use the synth_design command. Add the following to your Tcl
synth_design -top sys_integration_top
Because you created an in-memory project and set the target part, defining the target part is not needed here; however, you must provide the top-level module name with the
The various Verilog files read into the in-memory design in Step 1: Reading Design Source Files do not reference other files via an
`includestatement. If they did, you would need to define the
`includesearch directories with the
After synthesis, you should generate a design checkpoint to save the results. This way you can restore the synthesized design at any time without running synthesis again.
- Add the following
write_checkpointcommand to your Tcl script:
write_checkpoint -force post_synth.dcp
-forceoption is used to overwrite the checkpoint file if it already exists.
You can also generate any needed reports at this point, such as a post-synthesis timing summary report.
- Add the following line to your Tcl
report_timing_summary -file timing_syn.rpt
This command creates a comprehensive timing report for the design and writes the report to a file.