In the Project Mode, the Vivado Design Suite manages the details of synthesis and
implementation runs, using run strategies and maintains the state of the design.
Therefore, you will use the
launch_runs command to
run synthesis and implementation in project-based designs.
- Add the following line to your Tcl
By default, a synthesis run called synth_1 is created for every project. You can also manually create new runs using the
create_runcommand, and configure run properties using the
set_propertycommand. See the Vivado Design Suite User Guide: Design Flows Overview (UG892) for more information on creating and configuring runs.
After the synthesis run has completed, you can launch an implementation run. However, because the implementation run is dependent on the completion of the synthesis run, you must use the
wait_on_runcommand to hold your Tcl script until synthesis is complete.
- Add these two lines to your
wait_on_run synth_1 launch_runs impl_1 -to_step write_bitstream
When the synthesis run, synth_1, completes, the implementation run, impl_1, begins. Implementation is a multi-step process that begins with netlist optimization, runs through placement and routing, and can even include generating the bitstream for the Xilinx FPGA.
-to_stepoption that you added to your Tcl script indicates that implementation should include generating the bitstream for the device. By default, implementation does not include that step. See the Vivado Design Suite User Guide: Implementation (UG904) for more information.Tip: Alternatively, you can use the
write_bitsteamcommand; this requires that you open the implementation run first using the
Just as implementation needed to wait on synthesis to complete, wait for your Tcl script to allow implementation to complete before generating any reports, or exiting.
- Add the
wait_on_runcommand to your Tcl script, to wait for the implementation run to complete:
The script will wait until the implementation run completes before continuing.