Dynamic Function eXchange (DFX) in Xilinx® FPGAs, SoCs, and ACAPs introduces new design requirements compared to traditional solutions. These requirements include unique approaches to source and run management, as both bottom-up synthesis and multi-pass implementation are needed. Before 2021, only non-project Tcl-based and RTL project-based solutions have been available in Vivado® . Vivado® 2021.2 introduced an IP-centric project-based environment, which includes new capabilities for block designs and other aspects of IP integrator.
This tutorial is intended to summarize the Vivado tool flow, from project creation to partial bitstream creation for Zynq® UltraScale+™ MPSoC and RFSoC targets using the Block Design Container feature in IP integrator. This fundamental flow can be used to apply to Virtex and Kintex® UltraScale™ and UltraScale+™ targets as well. The next lab covers the equivalent solution for Versal® ACAP targets.
The Dynamic Function eXchange IP integrator Project Flow inserts the key requirements of DFX into the existing Vivado® project solution, accessible within the Vivado IDE as well as via Tcl commands. Key requirements include:
- Creating Block Design Containers (BDC) to identify hierarchy in a project.
- Defining BDCs as Reconfigurable Partitions within the design hierarchy.
- Populating a set of Reconfigurable Modules for each Reconfigurable Partition.
- Creating a set of top-level and module-level synthesis runs.
- Creating a set of related implementation runs.
- Managing dependencies as sources, constraints, or options are modified.
- Checking rules and results.
- Verifying configurations.
- Generating compatible sets of full and partial bitstreams.
- Delivering full and partial images to the Zynq UltraScale+ target device.
Like with most everything within the Vivado® IDE, the features and tasks for Dynamic Function eXchange you see are driven behind the scenes by Tcl commands. One of the key goals for DFX project support is to be able to work seamlessly between GUI and script and command line on the same project. You can examine the specific Tcl commands called by examining the Vivado® journal file for this project. This can be seen by selecting File > Open Journal File. These Tcl commands are not documented in this user guide at this point. Also supported is the ability to export project scripts using the Write Project Tcl option. Additional information for each command can be found using the –help option of each command.
DFX Project Tutorial within IP Integrator
The design supplied here specifically targets the ZCU102 development system. The entire design can be processed completely or partially via scripts. The key scripts found in the project archive are:
run_all.tcl – This script runs the entire flow from
block design creation to bitstream generation and hardware export. This
includes all the steps managed by the DFX Wizard. It calls multiple scripts,
in this order:
- create_top_bd.tcl – This script creates the static block design and all IP for a completely flat design. One could run this script and then launch the implementation to generate a standard (non-DFX) implementation for the ZCU102
- create_rp1_bdc.tcl – This script creates two levels of hierarchy and converts one to be a block design container.
- enable_dfx_bdc.tcl – This script turns the standard BDC into a DFX BDC.
- create_rp1rm2.tcl – This script creates a new RM for the existing DFX BDC.
- run_impl.tcl – This script is the remainder of the flow. This script creates a top-level wrapper, adds design constraints, and walks through the DFX Wizard. It then generates all outputs for the design, from IP results to synthesis and implementation runs, then creates bitstreams and XSA files for hardware handoff.
This tutorial can be run completely via a script by sourcing the run_all.tcl script in a Vivado® Tcl shell. Each sub-section can also be run individually using the remaining Tcl scripts listed above. The tutorial as described will manually run through most steps to show what is happening throughout the flow. Sub-section scripts will be noted along the way. This tutorial does not show iterative interaction with the IPI design.