This tutorial covers the Dynamic Function eXchange (DFX) software support in Vivado® Design Suite release 2021.1.
7 Series Basic DFX Flow and UltraScale and UltraScale+ Basic DFX Flow step through basic information about the current DFX design flow, example Tcl scripts, and results within the Vivado integrated design environment (IDE). You run scripts for part of the lab and work interactively with the design for other parts. You can also script the entire flow and a completed script is included with the design files. These labs focus specifically on the software flow from RTL to bitstream, demonstrating how to process a (DFX design. Lab 2 also applies to UltraScale+™ devices.
DFX RTL Project Flow guides you through the project flow within the Vivado® IDE, from establishing the design using the DFX Wizard to synthesis, iteration runs, and then iterating the design. Vivado Debug and the DFX Project Flow also walks you through the project flow, but includes adding IP, debug cores, and debugging through the Vivado® Hardware Manager.
DFX Controller IP for 7 Series Devices, DFX Controller IP for UltraScale Devices, and DFX Controller IP for UltraScale+ Devices are designed to show the fundamental details and capabilities of the DFX Controller IP in the Vivado Design Suite. Managing partial bitstreams is one of the new design requirements introduced by DFX: designers plan for when partial bitstreams are required, where they are stored, how they are delivered to the configuration engine, and how the static design behaves before, during and after the delivery of a new partial bitstream. The DFX Controller IP is designed to help users solve these challenges.
Nested Dynamic Function eXchange shows the flow and methodologies for nesting a reconfigurable partition inside a reconfigurable partition. This extension to the DFX solution further extends the flexibility of dynamic reconfiguration in any UltraScale or UltraScale+ device.
Abstract Shell for Dynamic Function eXchange shows how users can improve Vivado compile time by stripping away the bulk of the static logic and parallelizing runs when using UltraScale+ devices in non-project mode. This feature also safeguards static design information when applying DFX in multi-user environments.
DFX BDC Project Flow in IP Integrator for Zynq UltraScale+and DFX BDC Project Flow in IP Integrator for Versal show the methodologies and capabilities of building and processing DFX designs within IP integrator. Block Design Containers allow users to build Reconfigurable Modules as block designs inserted in a top-level block design. These labs show examples targeting Zynq® UltraScale+™ and Versal® , but all architectures are supported.
In addition to the tutorial examples in this document, many more can be found on the Xilinx GitHub. Examples showing new features and capabilities for Versal devices can be found at here. While the specific details about the Versal architecture do not apply to prior architectures, the design flow using Block Design Containers through IP integrator applies to all architectures. Additional targeted examples can be found at here.