Step 10: Implement the Configurations and Generate Bitstreams - 2021.2 English

Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947)

Document ID
UG947
Release Date
2022-04-18
Version
2021.2 English

With all design sources now added to the project, and all settings complete for a DFX design, it is time to implement the design.

  1. In the Design Runs window, right-click on child_0_impl_1 and select Launch Runs. Click OK to start the process.

    This action will launch all runs necessary to implement both parent and child configurations, in the proper order.

    • Out-of-context (OOC) synthesis will be run for the two RMs. These are launched in parallel as they do not depend on each other.
    • Synthesis of the top-level design launches with the OOC runs completely. This completes very quickly as the top level is nothing more than IO insertion plus two black boxes.
    • The parent-run is implemented first. This is a standard Vivado┬« implementation run that applies DFX constraints. At the end of the run, multiple design checkpoints are written:
      1. A standard placed and routed checkpoint for the full design.
      2. A module-level checkpoint for the RM rp1rm1 was also placed and routed.
      3. A static-only design checkpoint, with all placement and routing locked, and a black box for rp1.
    • The child run is run last, and it starts with the locked static-only checkpoint from the parent-run.
  2. Select Cancel on the resulting dialog box when implementation completes. Synthesized and implemented design checkpoints can be viewed at this point.
  3. Shift-click in the Design Runs window to select both impl_1 and child_0_impl_1, then right-click to select Generate Device Image. Click OK in the resulting dialog to continue.

This will create full device bitstreams for both configurations, and partial bitstreams for rm1 and rm2 Reconfigurable Modules.