Before launching synthesis, take a look at the naming convention that inserts the Debug Hubs necessary for the Vivado Debug solution.
- Open mult.v and examine the port list in this file.
The port list includes twelve ports that start with S_BSCAN_. These ports are used to connect the Debug Hubs that are inserted in the static and reconfigurable parts of the design. The insertion of these hubs is automatic. Connections are automatically made as long as the port list matches this naming convention.CAUTION:These exact port names must be used to have the inference occur. If the port names differ at all, then the attributes shown in the comments of these RTL files must be used to assign the new signal names to the debug properties as indicated.
With the design from section one open in the Vivado IDE, take a look at the Design Runs window. The top-level design synthesis run (synth_1) and the parent implementation run (impl_1) are marked “active.” The Flow Navigator actions apply to these active runs, so clicking on Run Synthesis or Run Implementation will pull the design through only these runs, as well as the OOC synthesis runs needed to complete them. You could select the child implementation run, right-click, and select Launch Runs to pull through the entire flow, but we’ll run synthesis separately here.
- In the Flow Navigator, click Run Synthesis. When
synthesis completes, select Open Synthesized Design.
This action synthesizes all OOC modules, followed by synthesis of the top level design. This is no different than any design with OOC modules (IP or otherwise).
- Open the schematic for the post-synthesis view to see the insertions
performed during synthesis.
In the top level design, see that a dbg_hub instance was inserted. Its sl_* ports are connected to the VIO debug core at the top level. Next, descend into the my_math hierarchy to see that another dbg_hub instance has been inserted, with its sl_* ports connected to the ILA debug core in that module. Note that this Reconfigurable Module is the multiplier, as this is the schematic view of the active parent run.Figure 1. dbg_hub_1 Inserted within the mult RM
- Select Vivado in
floorplanning mode. Then in the Netlist window, right click on the my_math
instance and select . Create a Pblock wherever you’d like. In the dialog box that
appears, keep the name pblock_my_math and leave only SLICE, DSP and BRAM
resource types checked.Figure 2. Drawing a Pblock for the my_math RP
If the region you have selected does not have enough resources of any particular type, these resource types will appear in red in the Statistics tab of the Pblock Properties window. Make adjustments as necessary, then save the floorplan. Remember, each RM contains an ILA core, which will require BRAM. Also, this design has a high number of control sets, so the region required may be a little bigger than expected. An area of at least 3000 CLBs plus a column of BRAM is suggested.
- Run DFX-specific design rule checks by selecting OK
to run.Figure 3. Checking DFX DRCs
Fix any errors that may appear. Advisory messages might appear for certain devices with suggestions on how to improve the quality of the given Pblocks.Tip: Run DFX Design Rule Checks early and often.
. To save time, you can deselect all checkboxes other than the one
for Dynamic Function eXchange. Click
- Save your constraints by clicking Save Constraints in the top toolbar.