Adding Multicycle Path Constraints - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
Release Date
2021.2 English

Multicycle path exceptions must reflect the design functionality and must be applied on paths that do not have an active clock edge at every cycle, on either the source clock, the destination clock or both clocks. The path multiplier is expressed in terms of clock cycles, either based on the source clock when the -start option is used, or the destination clock when the -end option is used. This is particularly convenient for modifying the setup and hold relationships between the startpoint and endpoint independently of the clock period value.

The hold relationships are always tied to the setup ones. Consequently, in most cases, the hold relationship also needs to be separately adjusted after the setup one has been modified. This is why a second constraint with the -hold option is needed. The main exception to this rule is for synchronous CDC paths between phase-shifted clocks: only setup needs to be modified.