BUFG_GT with Dynamic Divider - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2021.2 English

In UltraScale devices, the BUFG_GT buffer simplifies GT clocking. Because the BUFG_GT includes dynamic division capabilities, MMCMs are no longer required to perform simple integer divides on GT output clocks. This saves clocking resources and provides an improved low skew clock path when both a divided GT*_CHANNEL output clock and full-rate clock are required.

You can use the BUFG_GT global clock buffer for GT interfaces where the user logic operates at half the clock frequency of the internal PCS logic or for PCIe interfaces where the GT*_CHANNEL needs to generate multiple clock frequencies for user_clk, sys_clk, and pipe_clk. The following figure compares clocking requirements between 7 series and UltraScale devices for a single-lane GT interface where the frequency of TXUSRCLK2 is equal to half of the frequency of TXUSRCLK.

Figure 1. Clocking Requirements Comparison

You can use any output clock of the GT*_CHANNELs within a Quad or any reference clock generated by an IBUFDS_GTE3/ODIV2 pin within a Quad to drive any of the 24 BUFG_GT buffers located in the same clock region. A BUFG_GT_SYNC is always required to synchronize reset and clear of BUFG_GTs driven by a common clock source.

Note: The Vivado tools automatically insert the BUFG_GT_SYNC primitive if it is not present in the design.

Some applications still require the use of an MMCM to generate complex non-integer clock division of the GT output clocks or the IBUFDS_GTE3/ODIV2 reference clock. In these cases, a BUFG_GT must directly drive the MMCM. By default, the placer tries to place the MMCM on the same clock region row as the BUFG_GT. If other MMCMs try to use the same MMCM site, you must verify that the automated MMCM placement is still as close as possible to the BUFG_GT to avoid wasting clocking resources due to long routes.