After the device completes configuration, a sequence of events occurs in which the device completes the configuration state and enters into general operation. In most configuration sequences, one of the last steps is the deassertion of the Global Set Reset (GSR), followed by the deassertion of the Global Enable (GWE) signal. When this happens, the design is in a known initial state and is then released for operation.
If this release point is not synchronized to the given clock domain or if the clock is operating at a faster time than the GWE can safely be released, portions of the design can go into an unknown state. For some designs, this does not matter. In other designs, this can cause the design to become unstable or to incorrectly process the initial data set.
If the design must start up in a known state, Xilinx recommends that you take action to control the start-up synchronization process using any of the following methods:
- Use clock enables, local reset (synchronized), or both, on critical parts of the design, such as a state machine, to ensure that the start-up of those portions of the design are controlled and known.
Use instantiated clock buffer components with clock enable capability.
Delay the reset release by as many cycles as needed before enabling the design clock. The following example shows how to delay the first design clock edge after the reset is released in an UltraScale device. By setting ASYNC_REG=TRUE on the synchronizer registers, all registers are placed in a single SLICE and therefore, do not need to be driven by a global clock resource. To prevent clock buffer insertion on the synchronizer clock, use the CLOCK_BUFFER_TYPE=NONE property on the input clock port.Figure 1. Reset Synchronization and Delay for Safe Clock Startup Example
When using an MMCM, you can select the Safe Clock Startup option from the Clocking Wizard to ensure that design clocks are enabled only after they are stable and reliable.
The following example shows the synchronization stages of an UltraScale device MMCM LOCKED signal connected to the CE pin of the BUFGCE, which drives the user logic. A second BUFGCE is connected in parallel to the high fanout BUFGCE (user clock) and is dedicated to the logic controlling the BUFGCE/CE pin. This topology helps timing closure on the BUFGCE/CE in UltraScale devices by minimizing the clock skew between the synchronizer and the BUFGCE pin.Figure 2. MMCM Safe Clock Startup Example
Tip: If the MMCM or PLL compensation mode is set to ZHOLD or BUF_IN, all clocks from CLKOUT0 are grouped with the feedback clock and use the same CLOCK_ROOT. If this introduces timing violations on BUFGCE/CE, create a CLOCK_DELAY_GROUP constraint between the high fanout clock and the feedback clock only. Optionally, you can also set a USER_CLOCK_ROOT constraint on the low fanout clock net to constrain the loads to the same clock region as the MMCM. For 7 series devices, the second clock buffer is usually not needed for helping timing closure due to the different clocking architecture.