Fixing Issues Flagged by report_methodology - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
UG949
Release Date
2021-11-19
Version
2021.2 English

The report_methodology command reports additional constraints and timing analysis issues, which you must carefully review before and after running the place and route tools. This section describes the main XDC and TIMING categories of checks, along with their relative impact on timing closure and hardware stability. You must focus on resolving the checks that impact timing closure first.

For more information on some of these checks, see this link in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906). Also, see the Adoption Of The Methodology Report blog series for more information on how report_methodology helps to resolve issues and save time.

Important: To increase visibility, the summary of the methodology violations is also included in the timing summary text report, because addressing these issues is critical for having proper signoff timing.