Further Refining Control Signal Activity After Running Power Analysis - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
UG949
Release Date
2021-11-19
Version
2021.2 English

When SAIF-based annotation has not been used for accurate power analysis, you can fine-tune the power analysis after doing the first level analysis. For more information, see Further Refining Control Signal Activity in the Vivado Design Suite User Guide: Power Analysis and Optimization (UG907).