Identifying Which Clocks Must Be Created - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2021.2 English

Begin by loading the post synthesized netlist or checkpoint into the Vivado IDE. In the Tcl Console, use the reset_timing command to ensure that all timing constraints are removed.

Use the report_clock_networks Tcl command to create a list of all the primary clocks that must be defined in the design. The resulting list of clock networks shows which clock constraints should be created. Use the Timing Constraints Editor to specify the appropriate parameters for each clock.