Identifying the Clocks Related to Each Port - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
UG949
Release Date
2021-11-19
Version
2021.2 English

Before defining the I/O delay constraint, you must identify which clocks are related to each port. You can identify the clocks using the methods described in the following sections.