Inserting, Deleting, or Editing ILA Cores on an Implemented Netlist - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2021.2 English

If you want to add, delete, or modify ILA cores (for example, resizing probe width, changing the data depth, etc.), Xilinx recommends that you use the Incremental Compile flow. The Incremental Compile flow for debug cores operates on a synthesized design or checkpoint (DCP) and uses a reference implemented checkpoint, ideally from a previous implementation run. This approach might save you time versus a complete re-implementation of the design.

For information on using the Incremental Compile flow to insert, delete, or edit ILA cores, see this link in the Vivado Design Suite User Guide: Programming and Debugging (UG908).