OSERDESE3 Clocking - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2021.2 English

For OSERDESE3 clocking in UltraScale and UltraScale+ devices, maximum skew requirements exist between the high-speed clock and divided clock pins. To meet the maximum skew requirements, Xilinx recommends using parallel global clock buffers where one of the global clock buffers is a BUFGCE_DIV. This removes the additional clock uncertainty between the two outputs of the MMCM.

In the following figure, the left side shows a suboptimal configuration that uses two separate outputs of the MMCM. The right side of the figure shows the optimal configuration that uses a single MMCM output and the BUFGCE_DIV cell, which provides the divided clock using the BUFGCE_DIVIDE property.

Note: The high-speed clock does not need to be driven by a BUFGCE. Alternatively, you can use BUFGCE_DIV with a BUFGCE_DIVIDE property setting of 1.
Figure 1. Suboptimal to Optimal Clocking Topologies for OSERDESE3